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M
Features
* Multiplexed Inputs: 1, 2, 6 or 8 channels * 8 Gain Selections: - +1, +2, +4, +5, +8, +10, +16 or +32 V/V * Serial Peripheral Interface (SPITM) * Rail-to-Rail Input and Output * Low Gain Error: 1% (max) * Low Offset: 275 V (max) * High Bandwidth: 2 to 12 MHz (typ) * Low Noise: 10 nV/Hz @ 10 kHz (typ) * Low Supply Current: 1.0 mA (typ) * Single Supply: 2.5V to 5.5V
MCP6S21/2/6/8
Description
The Microchip Technology Inc. MCP6S21/2/6/8 are analog Programmable Gain Amplifiers (PGA). They can be configured for gains from +1 V/V to +32 V/V and the input multiplexer can select one of up to eight channels through an SPI port. The serial interface can also put the PGA into shutdown to conserve power. These PGAs are optimized for high speed, low offset voltage and single-supply operation with rail-to-rail input and output capability. These specifications support single supply applications needing flexible performance or multiple inputs. The one channel MCP6S21 and the two channel MCP6S22 are available in 8-pin PDIP, SOIC and MSOP packages. The six channel MCP6S26 is available in 14-pin PDIP, SOIC and TSSOP packages. The eight channel MCP6S28 is available in 16-pin PDIP and SOIC packages. All parts are fully specified from -40C to +85C.
Single-Ended, Rail-to-Rail I/O, Low Gain PGA
Typical Applications
* * * * * * A/D Converter Driver Multiplexed Analog Applications Data Acquisition Industrial Instrumentation Test Equipment Medical Instrumentation
Block Diagram
VDD CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CS SI SO SCK + MUX RF Gain Switches SPITM Logic POR VSS VREF 8 RG Resistor Ladder (RLAD )
Package Types
MCP6S21 PDIP, SOIC, MSOP
VOUT 1 CH0 2 VREF 3 VSS 4 8 VDD 7 SCK 6 SI 5 CS
VOUT
MCP6S22 PDIP, SOIC, MSOP
VOUT 1 CH0 2 CH1 3 VSS 4 8 VDD 7 SCK 6 SI 5 CS
MCP6S26 PDIP, SOIC, TSSOP
VOUT 1 CH0 2 CH1 3 CH2 4 CH3 5 CH4 6 CH5 7 14 VDD 13 SCK 12 SO 11 SI 10 CS 9 VSS 8 VREF
MCP6S28 PDIP, SOIC
VOUT 1 CH0 2 CH1 3 CH2 4 CH3 5 CH4 6 CH5 7 CH6 8 16 VDD 15 SCK 14 SO 13 SI 12 CS 11 VSS 10 VREF 9 CH7
2003 Microchip Technology Inc.
DS21117A-page 1
MCP6S21/2/6/8
1.0 ELECTRICAL CHARACTERISTICS PIN FUNCTION TABLE
Name Function
Absolute Maximum Ratings
VDD - VSS .........................................................................7.0V All inputs and outputs....................... VSS - 0.3V to V DD +0.3V Difference Input voltage ........................................ |VDD - VSS| Output Short Circuit Current...................................continuous Current at Input Pin .............................................................2 mA Current at Output and Supply Pins ................................ 30 mA Storage temperature .....................................-65C to +150C Junction temperature .................................................. +150C ESD protection on all pins (HBM;MM).................. 2 kV; 200V Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
VOUT CH0-CH7 VSS VDD SCK SI SO CS VREF
Analog Output Analog Inputs Negative Power Supply Positive Power Supply SPI Clock Input SPI Serial Data Input SPI Serial Data Output SPI Chip Select External Reference Pin
DC CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, TA = +25C, VDD = +2.5V to +5.5V, VSS = GND, VREF = VSS, G = +1 V/V, Input = CH0 = (0.3V)/G, CH1 to CH7 = 0.3V, R L = 10 k to VDD /2, SI and SCK are tied low and CS is tied high. Parameters Amplifier Input Input Offset Voltage Input Offset Voltage Drift Power Supply Rejection Ratio Input Bias Current Input Bias Current over Temperature Input Impedance Input Voltage Range Amplifier Gain Nominal Gains DC Gain Error DC Gain Drift Internal Resistance Internal Resistance over Temperature Amplifier Output DC Output Non-linearity G = +1 G +2 Maximum Output Voltage Swing VONL VONL V OH, VOL -- -- VSS+20 VSS+60 Short-Circuit Current IO(SC) -- 0.003 0.001 -- -- 30 -- -- VDD-100 VDD -60 -- mA % of FSR VOUT = 0.3V to VDD - 0.3V, VDD = 5.0V % of FSR VOUT = 0.3V to VDD - 0.3V, VDD = 5.0V mV G +2; 0.5V output overdrive G +2; 0.5V output overdrive, VREF = VDD/2 G = +1 G +2 G = +1 G +2 G gE gE G/TA G/TA RLAD RLAD /TA -- -0.1 -1.0 -- -- 3.4 -- 1 to 32 -- -- 0.0002 0.0004 4.9 +0.028 -- +0.1 +1.0 -- -- 6.4 -- V/V % % %/C %/C k %/C +1, +2, +4, +5, +8, +10, +16 or +32 VOUT 0.3V to VDD - 0.3V VOUT 0.3V to VDD - 0.3V TA = -40 to +85C TA = -40 to +85C (Note 1) (Note 1) TA = -40 to +85C VOS VOS/TA PSRR IB IB ZIN VIVR -275 -- 70 -- -- -- VSS-0.3 -- 4 85 1 -- 1013||15 -- +275 -- -- -- 250 -- VDD+0.3 V V/C dB pA pA ||pF V G = +1, VDD = 4.0V TA = -40 to +85C G = +1 (Note 1) CHx = V DD/2 TA = -40 to +85C, CHx = VDD/2 Sym Min Typ Max Units Conditions
Note 1: RLAD (RF + RG in Figure 4-1) connects V REF, VOUT and the inverting input of the internal amplifier. The MCP6S22 has VREF tied internally to VSS, so VSS is coupled to the internal amplifier and the PSRR spec describes PSRR+ only. We recommend the MCP6S22's VSS pin be tied directly to ground to avoid noise problems. 2: IQ includes current in RLAD (typically 60 A at VOUT = 0.3V). Both IQ and IQ_SHDN exclude digital switching currents. 3: The output goes Hi-Z and the registers reset to their defaults; see Section 5.4, "Power-On Reset".
DS21117A-page 2
2003 Microchip Technology Inc.
MCP6S21/2/6/8
DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, TA = +25C, VDD = +2.5V to +5.5V, VSS = GND, VREF = VSS, G = +1 V/V, Input = CH0 = (0.3V)/G, CH1 to CH7 = 0.3V, R L = 10 k to VDD /2, SI and SCK are tied low and CS is tied high. Parameters Power Supply Supply Voltage Quiescent Current Quiescent Current, Shutdown mode Power-On Reset POR Trip Voltage POR Trip Voltage Drift VPOR VPOR /T 1.2 -- 1.7 -3.0 2.2 -- V mV/C (Note 3) TA = -40C to+85C VDD IQ IQ_SHDN 2.5 0.5 -- -- 1.0 0.5 5.5 1.35 1.0 V mA A IO = 0 (Note 2) IO = 0 (Note 2) Sym Min Typ Max Units Conditions
Note 1: RLAD (RF + RG in Figure 4-1) connects V REF, VOUT and the inverting input of the internal amplifier. The MCP6S22 has VREF tied internally to VSS, so VSS is coupled to the internal amplifier and the PSRR spec describes PSRR+ only. We recommend the MCP6S22's VSS pin be tied directly to ground to avoid noise problems. 2: IQ includes current in RLAD (typically 60 A at VOUT = 0.3V). Both IQ and IQ_SHDN exclude digital switching currents. 3: The output goes Hi-Z and the registers reset to their defaults; see Section 5.4, "Power-On Reset".
AC CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, TA = +25C, VDD = +2.5V to +5.5V, VSS = GND, VREF = VSS, G = +1 V/V, Input = CH0 =(0.3V)/G, CH1 to CH7=0.3V, RL = 10 k to VDD/2, CL = 60 pF, SI and SCK are tied low, and CS is tied high. Parameters Frequency Response -3 dB Bandwidth Gain Peaking Total Harmonic Distortion plus Noise f = 1 kHz, G = +1 V/V f = 1 kHz, G = +4 V/V f = 1 kHz, G = +16 V/V f = 20 kHz, G = +1 V/V f = 20 kHz, G = +4 V/V f = 20 kHz, G = +16 V/V Step Response Slew Rate SR -- -- -- Noise Input Noise Voltage Input Noise Voltage Density Input Noise Current Density Eni eni ini -- -- -- -- 3.2 26 10 4 -- -- -- -- V P-P f = 0.1 Hz to 10 kHz (Note 2) f = 0.1 Hz to 200 kHz (Note 2) nV/Hz f = 10 kHz (Note 2) fA/Hz f = 10 kHz 4.0 11 22 -- -- -- V/s V/s V/s G = 1, 2 G = 4, 5, 8, 10 G = 16, 32 THD+N THD+N THD+N THD+N THD+N THD+N -- -- -- -- -- -- 0.0015 0.0058 0.023 0.0035 0.0093 0.036 -- -- -- -- -- -- % % % % % % VOUT = 1.5V 1.0VPK, VDD = 5.0V, BW = 22 kHz VOUT = 1.5V 1.0VPK, VDD = 5.0V, BW = 22 kHz VOUT = 1.5V 1.0VPK, VDD = 5.0V, BW = 22 kHz VOUT = 1.5V 1.0VPK, VDD = 5.0V, BW = 80 kHz VOUT = 1.5V 1.0VPK, VDD = 5.0V, BW = 80 kHz VOUT = 1.5V 1.0VPK, VDD = 5.0V, BW = 80 kHz BW GPK -- -- 2 to 12 0 -- -- MHz dB All gains; VOUT < 100 mVP-P (Note 1) All gains; VOUT < 100 mVP-P Sym Min Typ Max Units Conditions
Note 1: See Table 4-1 for a list of typical numbers. 2: Eni and eni include ladder resistance noise. See Figure 2-33 for eni vs. G data.
2003 Microchip Technology Inc.
DS21117A-page 3
MCP6S21/2/6/8
DIGITAL CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, TA = +25C, VDD = +2.5V to +5.5V, VSS = GND, VREF = VSS, G = +1 V/V, Input = CH0 = (0.3V)/G, CH1 to CH7 = 0.3V, RL = 10 k to VDD /2, CL = 60 pF, SI and SCK are tied low, and CS is tied high. Parameters SPI Inputs (CS, SI, SCK) Logic Threshold, Low Input Leakage Current Logic Threshold, High Amplifier Output Leakage Current Logic Threshold, Low Logic Threshold, High SPI Timing Pin Capacitance Input Rise/Fall Times (CS, SI, SCK) Output Rise/Fall Times (SO) CS high time SCK edge to CS fall setup time CS fall to first SCK edge setup time SCK Frequency SCK high time SCK low time SCK last edge to CS rise setup time CS rise to SCK edge setup time SI set-up time SI hold time SCK to SO valid propagation delay CS rise to SO forced to zero Channel and Gain Select Timing Channel Select Time tCH -- 1.5 -- s CHx = 0.6V, CHy =0.3V, G = 1, CHx to CHy select CS = 0.7VDD to VOUT 90% point CHx = 0.3V, G = 5 to G = 1 select, CS = 0.7VDD to VOUT 90% point CS = 0.7VDD to VOUT 90% point CPIN tRFI tRFO tCSH tCS0 tCSSC fSCK tHI tLO tSCCS tCS1 tSU tHD tDO tSOZ -- -- -- 40 10 40 -- 40 40 30 100 40 10 -- -- 10 -- 5 -- -- -- -- -- -- -- -- -- -- -- -- -- 2 -- -- -- -- 10 -- -- -- -- -- -- 80 80 pF s ns ns ns ns MHz ns ns ns ns ns ns ns ns MCP6S26 and MCP6S28 MCP6S26 and MCP6S28 SCK edge when CS is high VDD = 5V (Note 2) SCK edge when CS is high All digital I/O pins Note 1 MCP6S26 and MCP6S28 VIL IIL VIH -- V OL VOH 0 -1.0 0.7VDD -1.0 VSS VDD -0.5 -- -- -- -- -- -- 0.3VDD +1.0 VDD +1.0 VSS+0.4 VDD V A V A V V In Shutdown mode IOL = 2.1 mA, VDD = 5V IOH = -400 A Sym Min Typ Max Units Conditions
SPI Output (SO, for MCP6S26 and MCP6S28)
Gain Select Time Shutdown Mode Timing Out of Shutdown mode (CS goes high) to Amplifier Output Turn-on Time Into Shutdown mode (CS goes high) to Amplifier Output High-Z Turn-off Time POR Timing Power-On Reset power-up time Power-On Reset power-down time
tG
--
1
--
s
tON
--
3.5
10
s
tOFF
--
1.5
--
s
CS = 0.7VDD to VOUT 90% point
tRPU tRPD
-- --
30 10
-- --
s s
VDD = VPOR - 0.1V to VPOR + 0.1V, 50% VDD to 90% VOUT point VDD = VPOR + 0.1V to VPOR - 0.1V, 50% VDD to 90% VOUT point
Note 1: Not tested in production. Set by design and characterization. 2: When using the device in the daisy chain configuration, maximum clock frequency is determined by a combination of propagation delay time (tDO 80 ns), data input setup time (tSU 40 ns), SCK high time (tHI 40 ns), and SCK rise and fall times of 5 ns. Maximum fSCK is, therefore, 5.8 MHz.
DS21117A-page 4
2003 Microchip Technology Inc.
MCP6S21/2/6/8
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +2.5V to +5.5V, VSS = GND. Parameters Temperature Ranges Specified Temperature Range Operating Temperature Range Storage Temperature Range Thermal Package Resistances Thermal Resistance, 8L-PDIP Thermal Resistance, 8L-SOIC Thermal Resistance, 8L-MSOP Thermal Resistance, 14L-PDIP Thermal Resistance, 14L-SOIC Thermal Resistance, 14L-TSSOP Thermal Resistance, 16L-PDIP Thermal Resistance, 16L-SOIC JA JA JA JA JA JA JA JA -- -- -- -- -- -- -- -- 85 163 206 70 120 100 70 90 -- -- -- -- -- -- -- -- C/W C/W C/W C/W C/W C/W C/W C/W TA TA TA -40 -40 -65 -- -- -- +85 +125 +150 C C C (Note Note:) Sym Min Typ Max Units Conditions
Note 1: The MCP6S21/2/6/8 family of PGAs operates over this extended temperature range, but with reduced performance. Operation in this range must not cause TJ to exceed the Maximum Junction Temperature (150C).
CS tCH
CS tG
VOUT
0.6V 0.3V
VOUT
1.5V 0.3V
FIGURE 1-1: Diagram.
Channel Select Timing
FIGURE 1-3: Diagram.
Gain Select Timing
CS tON tOFF
VDD
VPOR - 0.1V
VPOR + 0.1V tRPU
V POR - 0.1V tRPD
VOUT
Hi-Z 0.3V
Hi-Z
VOUT
Hi-Z 0.3V 1.0 mA (typ) 500 nA (typ)
Hi-Z
ISS 500 nA (typ)
1.0 mA (typ)
ISS
FIGURE 1-2: PGA Shutdown timing diagram (must enter correct commands before CS goes high).
FIGURE 1-4: POR power-up and powerdown timing diagram.
2003 Microchip Technology Inc.
DS21117A-page 5
MCP6S21/2/6/8
tCSH CS tCSSC tLO SCK tSU tHD SI tDO SO (first 16 bits out are always zeros) tSOZ 1/fSCK tHI tSCCS tCS1 tCS0
FIGURE 1-5:
Detailed SPI Serial Interface Timing, SPI 0,0 mode.
tCSH
CS tCSSC tHI SCK tSU SI tDO SO (first 16 bits out are always zeros) tSOZ tHD 1/fSCK tLO tSCCS tCS1 tCS0
FIGURE 1-6:
Detailed SPI Serial Interface Timing, SPI 1,1 mode.
DS21117A-page 6
2003 Microchip Technology Inc.
MCP6S21/2/6/8
1.1
1.1.1
DC Output Voltage Specs / Model
IDEAL MODEL
VOUT (V)
The ideal PGA output voltage (V OUT) is:
VDD VDD-0.3 V2
EQUATION
V O_ideal = GV IN V REF = V SS = 0V
(see Figure 1-7). This equation holds when there are no gain or offset errors and when the VREF pin is tied to a low impedance source (<< 0.1) at ground potential (VSS = 0V).
V
_l i V near O _i de al
where: G is the nominal gain
V
O
O
UT
0.3 0 0 0.3 G VDD - 0.3 VDD G G
V1 VIN (V)
1.1.2
LINEAR MODEL
The PGA's linear region of operation, including offset and gain errors, is modeled by the line VO_linear, shown in Figure 1-7.
FIGURE 1-7: Output Voltage Model with the standard condition VREF = VSS = 0V. 1.1.3 OUTPUT NON-LINEARITY
EQUATION
V O_linear = G ( 1 + g E ) ( V IN - 0.3V + V OS ) + 0.3V V REF = V SS = 0V The endpoints of this line are at VO_ideal = 0.3V and VDD-0.3V. The gain and offset specifications referred to in the electrical specifications are related to Figure 1-7, as follows:
Figure 1-8 shows the Integral Non-Linearity (INL) of the output voltage.
EQUATION
INL = V OUT - V O_linear The output non-linearity specification in the electrical specifications is related to Figure 1-8 by:
EQUATION
V2 - V1 g E = 100% ------------------------------------G ( V DD - 0.6V ) V1 G = +1 V OS = -----------------------G ( 1 + gE ) g E G T A = --------T A
EQUATION
max { V 4, V 3 } V ONL = -------------------------------V DD - 0.6V
INL (V)
V4 0 V3 VIN (V)
0
0.3 G
VDD - 0.3 VDD G G
FIGURE 1-8: Output Voltage INL with the standard condition VREF = VSS = 0V.
2003 Microchip Technology Inc.
DS21117A-page 7
MCP6S21/2/6/8
1.1.4 DIFFERENT VREF CONDITIONS
Some of the plots in Section 2.0, "Typical Performance Curves", have the conditions VREF = VDD/2 or VREF = VDD. The equations and figures above are easily modified for these conditions. The ideal VOUT becomes:
EQUATION
V O_ideal = V REF + G ( V IN - V RE F ) V DD V RE F > V SS = 0V The complete linear model is:
EQUATION
V O_linear = G ( 1 + g E ) ( V IN - V IN_L + V OS ) + 0.3V where the new VIN endpoints are:
EQUATION
0.3V - V REF V IN_L = ----------------------------G + V REF V D D - 0.3V - V REF V IN_R = ---------------------------------------------G + V REF The equations for extracting the specifications do not change.
DS21117A-page 8
2003 Microchip Technology Inc.
MCP6S21/2/6/8
2.0
Note:
TYPICAL PERFORMANCE CURVES
The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25C, VDD = +5.0V, VSS = GND, VREF = VSS, G= +1 V/V, Input = CH0 = (0.3V)/G, CH1 to CH7 = 0.3V, RL = 10 k to VDD/2, and CL = 60 pF.
Percentage of Occurrences
22% 20% 18% 16% 14% 12% 10% 8% 6% 4% 2% 0%
Percentage of Occurrences
420 Samples G = +1
18% 16% 14% 12% 10% 8% 6% 4% 2% 0% -0.0006 -0.0005 -0.0004 -0.0003 -0.0002 -0.0001 0.0000 0.0001 0.0002 0.0003 0.0004 0.0005 0.0006
240 420 Samples G = +1 TA = -40 to +125C
0.000
-0.040
-0.036
-0.032
-0.028
-0.024
-0.020
-0.016
-0.012
-0.008
-0.004
0.004
DC Gain Error (%)
DC Gain Drift (%/C)
FIGURE 2-1:
18%
DC Gain Error, G = +1.
FIGURE 2-4:
24% 22% 20% 18% 16% 14% 12% 10% 8% 6% 4% 2% 0%
DC Gain Drift, G = +1.
Percentage of Occurrences
Percentage of Occurrences
16% 14% 12% 10% 8% 6% 4% 2% 0%
420 Samples G +2
420 Samples G +2 TA = -40 to +125C
0.0000
0.0004
0.0008
0.0012
0.0016
200
-0.0020
-0.0016
-0.0012
-0.0008
DC Gain Error (%)
DC Gain Drift (%/C)
FIGURE 2-2:
22% 20% 18% 16% 14% 12% 10% 8% 6% 4% 2% 0%
DC Gain Error, G +2.
FIGURE 2-5:
20%
DC Gain Drift, G +2.
Percentage of Occurrences
Percentage of Occurrences
420 Samples TA = -40 to +125C
18% 16% 14% 12% 10% 8% 6% 4% 2% 0%
360 Samples VDD = 4.0 V G = +1
0.023
0.024
0.025
0.026
0.027
0.028
0.029
0.030
0.031
-0.0004
-0.5
-0.4
-0.3
-0.2
-0.1
0
40
-80
-40
80
120
-240
-200
-160
-120
Ladder Resistance Drift (%/C)
Input Offset Voltage (V)
FIGURE 2-3:
Ladder Resistance Drift.
FIGURE 2-6: VDD = 4.0V.
Input Offset Voltage,
2003 Microchip Technology Inc.
DS21117A-page 9
160
0.0020
0.0
0.1
0.2
0.3
0.4
0.5
MCP6S21/2/6/8
Note: Unless otherwise indicated, TA = +25C, VDD = +5.0V, VSS = GND, VREF = VSS, G= +1 V/V, Input = CH0 = (0.3V)/G, CH1 to CH7 = 0.3V, RL = 10 k to VDD/2, and CL = 60 pF.
200 G = +1 22% 420 Samples TA = -40 to +125C G = +1
Percentage of Occurrences
Input Offset Voltage (V)
150 100 50 0 -50 -100 -150 -200 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD = +5.5 VDD = +2.5
20% 18% 16% 14% 12% 10% 8% 6% 4% 2% 0%
10
12
14
-16
-14
-12
-10
VREF Voltage (V)
Input Offset Voltage Drift (V/C)
FIGURE 2-7: VREF Voltage.
0.01
Input Offset Voltage vs.
FIGURE 2-10:
Input Offset Voltage Drift.
VOUT = 0.3V to VDD -0.3V VONL/G, G = +1
0.0100% VDD = +5.5 V
DC Output Non-Linearity, Input Referred (% of FSR)
DC Output Non-Linearity, Input Referred (%)
0.001 VONL/G, G = +2 0.0001
VONL/G, G = +1 0.0010%
VONL/G, G
+4
VONL/G, G 0.0001%
+2
0.00001 2.5 3.0 3.5 4.0 4.5 5.0 5.5
1
Power Supply Voltage (V)
Output Voltage Swing (VP-P)
FIGURE 2-8: Supply Voltage.
1000
DC Output Non-Linearity vs.
FIGURE 2-11: Output Swing.
12 11 10 9 8 7 6 5 4 3 2 1 0
DC Output Non-Linearity vs.
Input Noise Voltage Density (nV/ Hz)
100
10
1
0.1
1
10
100
1000
10000
100000
0.1
1
10
100
1k
10k
100k
Input Noise Voltage Density (nV/ Hz)
f = 10 kHz
1
2
4
5
8
10
16
32
Frequency (Hz)
Gain (V/V)
FIGURE 2-9: vs. Frequency.
Input Noise Voltage Density
FIGURE 2-12: vs. Gain.
Input Noise Voltage Density
DS21117A-page 10
2003 Microchip Technology Inc.
16
0
2
4
6
-8
-6
-4
-2
8
10
MCP6S21/2/6/8
Note: Unless otherwise indicated, TA = +25C, VDD = +5.0V, VSS = GND, VREF = VSS, G= +1 V/V, Input = CH0 = (0.3V)/G, CH1 to CH7 = 0.3V, RL = 10 k to VDD/2, and CL = 60 pF.
Power Supply Rejection Ratio (dB)
120 110 100 90 80 70 -50 -25 0 25 50 75 100 125 100 90 80 70 60 50 40 VDD = 5.5 V VDD = 2.5 V Input Referred
Power Supply Rejection Ratio (dB)
10
10
100
100
1k
1000
10k
10000
100k
100000
Ambient Temperature (C)
Frequency (Hz)
FIGURE 2-13: Temperature.
1,000
PSRR vs. Ambient
FIGURE 2-16:
PSRR vs. Frequency.
10,000
Input Bias Current (pA)
Input Bias Current (pA)
CH0 = VDD VDD = 5.5 V
VDD = 5.5 V
1,000 TA = +125C 100 TA = +85C 10
100
10
1 55 65 75 85 95 105 115 125
1 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Ambient Temperature (C)
Input Voltage (V)
FIGURE 2-14: Input Bias Current vs. Ambient Temperature.
100
FIGURE 2-17: Voltage.
7 6
Input Bias Current vs. Input
Bandwidth (MHz)
G = +1 G = +4 G = +16 10
Gain Peaking (dB)
5 4 3 2 1
G = +1 G = +4 G = +16
1 10 100 1000
0 10 100 1000
Capacitive Load (pF)
Capacitive Load (pF)
FIGURE 2-15: Load.
Bandwidth vs. Capacitive
FIGURE 2-18: Load.
Gain Peaking vs. Capacitive
2003 Microchip Technology Inc.
DS21117A-page 11
MCP6S21/2/6/8
Note: Unless otherwise indicated, TA = +25C, VDD = +5.0V, VSS = GND, VREF = VSS, G= +1 V/V, Input = CH0 = (0.3V)/G, CH1 to CH7 = 0.3V, RL = 10 k to VDD/2, and CL = 60 pF.
40 30 20 10 0 -10 -20 G = +32 G = +16 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0.0 0.5 1.0 1.5 2.0
Quiescent Current (mA)
Gain (dB)
G = +10 G = +8 G = +5 G = +4
1.E+05 1.E+06
G = +2 G = +1
TA = +125C TA = +85C TA = +25C TA = -40C
1.E+07
1.E+08
100k
1M
10M
100M
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Frequency (Hz)
Supply Voltage (V)
FIGURE 2-19:
Gain vs. Frequency.
FIGURE 2-22: Supply Voltage.
Quiescent Current in Shutdown (A)
1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 -50 -25
Quiescent Current vs.
100%
Percentage of Occurrences
90% 80% 70% 60% 50% 40% 30% 20% 10% 0%
420 Samples VDD = 5.0 V
In Shutdown Mode VDD = 5.0 V
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
25
50
75
100
125
Quiescent Current in Shutdown (A)
Ambient Temperature (C)
FIGURE 2-20: Histogram of Quiescent Current in Shutdown Mode.
100
FIGURE 2-23: Quiescent Current in Shutdown Mode vs. Ambient Temperature.
40
Output Voltage Headroom (mV) VDD - VOH and V OL - VSS
Output Short Circuit Current (mA)
35 30 25 20 15 10 5 0 TA = +125C TA = +85C TA = +25C TA = -40C
VDD = +5.5V 10 VDD = +2.5V
1 0.1 1 10
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Output Current Magnitude (mA)
Power Supply Voltage (V)
FIGURE 2-21: Output Voltage Headroom vs. Output Current.
FIGURE 2-24: Output Short Circuit Current vs. Supply Voltage.
DS21117A-page 12
2003 Microchip Technology Inc.
MCP6S21/2/6/8
Note: Unless otherwise indicated, TA = +25C, VDD = +5.0V, VSS = GND, VREF = VSS, G= +1 V/V, Input = CH0 = (0.3V)/G, CH1 to CH7 = 0.3V, RL = 10 k to VDD/2, and CL = 60 pF.
1 Measurement BW = 80 kHz VOUT = 2 VP-P VDD = 5.0 V 1 Measurement BW = 80 kHz VOUT = 4 VP-P VDD = 5.0 V
THD + Noise (%)
THD + Noise (%)
0.1 G = +16 0.01 G = +4 G = +1 0.001 100
1.E+02 1.E+03 1.E+04 1.E+05
0.1 G = +16 0.01 G = +4
G = +1 1k 10k 100k 0.001 100
1.E+02 1.E+03 1.E+04 1.E+05
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
FIGURE 2-25: THD plus Noise vs. Frequency, VOUT = 2 VP-P.
80 250
FIGURE 2-28: THD plus Noise vs. Frequency, VOUT = 4 VP-P.
5.0
7.5
VDD = +5.0V
70 200 60 150
Normalized Input Voltage (50 mV/div)
50
Output Voltage (V)
4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0
0.00E+00 5.00E-07 1.00E-06 1.50E-06 2.00E-06 2.50E-06 3.00E-06 3.50E-06 4.00E-06 4.50E-06
5.5
100 40
4.5
50 30
3.5
20
0
2.5
GVIN
10 -50 0
-10
-20
VOUT, G = +1 G = +5 G = +32
-100
VOUT, G = +1 G = +5 G = +32
GVIN
1.5
0.5
-0. 5
-150
-1. 5
-200 -30 -2. 5 5.00E-06
-40 0.00E+00 2.00E-07 4.00E-07 6.00E-07 8.00E-07 1.00E-06 1.20E-06 1.40E-06 1.60E-06 1.80E-06
-250 2.00E-06
Time (200 ns/div)
Time (500 ns/div)
FIGURE 2-26: Response.
0.65 0.60
Small Signal Pulse
FIGURE 2-29: Response.
20
Large Signal Pulse
1.6
20
Chip Select Voltage (V)
15
1.4
15
Output Voltage (V)
0.55 0.50 0.45 0.40 0.35 0.30 0.25
0.00E+00
VOUT (CH0 = 0.6V, G = +1)
Output Voltage (V)
10
1.2 1.0 0.8 0.6 0.4 0.2 0.0
VOUT (CH0 = 0.3V, G = +5) CS
10
CS
5
5 0
5
5 0
0
0
CS
VOUT (CH1 = 0.3V, G = +1)
CS VOUT (CH0 = 0.3V, G = +1)
-5
-5
-10
-10
-15
-15
5.00E-07
1.00E-06
1.50E-06
2.00E-06
2.50E-06
3.00E-06
3.50E-06
4.00E-06
4.50E-06
-20 5.00E-06
0.00E+00
5.00E-07
1.00E-06
1.50E-06
2.00E-06
2.50E-06
3.00E-06
3.50E-06
4.00E-06
4.50E-06
-20 5.00E-06
Time (500 ns/div)
Time (500 ns/div)
FIGURE 2-27:
Channel Select Timing.
FIGURE 2-30:
Gain Select Timing.
2003 Microchip Technology Inc.
DS21117A-page 13
Chip Select Voltage (V)
Normalized Input Voltage (1V/div)
4.5
VDD = +5.0V
6.5
Output Voltage (10 mV/div)
MCP6S21/2/6/8
Note: Unless otherwise indicated, TA = +25C, VDD = +5.0V, VSS = GND, VREF = VSS, G= +1 V/V, Input = CH0 = (0.3V)/G, CH1 to CH7 = 0.3V, RL = 10 k to VDD/2, and CL = 60 pF.
1.0 0.9
25
10
20
Output Voltage Swing (VP-P)
Shutdown
Shutdown
Chip Select Voltage (V)
Output Voltage (mV)
0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0
0.0E+00 1.0E-06 2.0E-06
15
VDD = 5.5 V VDD = 2.5 V 1
10
5
CS
CS
0 -5
5 0
-10
-15
VOUT is "ON" (CH0 = 0.3V, G = +1)
3.0E-06 4.0E-06 5.0E-06 6.0E-06 7.0E-06 8.0E-06 9.0E-06
G = +1, +2 G = +4 to +10 G = +16, +32 0.1 10k
1.E+04 1.E+05 1.E+06 1.E+07
-20
-25 1.0E-05
100k
1M
10M
Time (1 s/div)
Frequency (Hz)
FIGURE 2-31: Shutdown Mode.
20%
Output Voltage vs.
FIGURE 2-33: Frequency.
6
Output Voltage Swing vs.
Percentage of Occurrences
18% 16% 14% 12% 10% 8% 6% 4% 2% 0%
420 Samples
VIN VOUT
Input, Output Voltage (V)
5 4 3 2 1 0 -1
0.0E+00 1.0E-03 2.0E-03
VDD = 5.0 V G = +1 V/V
1.60
1.64
1.68
1.72
1.76
1.80
1.84
1.88
3.0E-03
4.0E-03
5.0E-03
6.0E-03
7.0E-03
8.0E-03
9.0E-03
1.0E-02
POR Trip Voltage (V)
Time (1 ms/div)
FIGURE 2-32:
POR Trip Voltage.
FIGURE 2-34: The MCP6S21/2/6/8 family shows no phase reversal under overdrive.
DS21117A-page 14
2003 Microchip Technology Inc.
MCP6S21/2/6/8
3.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
MCP6S21
PIN FUNCTION TABLE
MCP6S22 MCP6S26 MCP6S28 Symbol Description
1 2 -- -- -- -- -- -- -- 3 4 5 6 -- 7 8
1 2 3 -- -- -- -- -- -- -- 4 5 6 -- 7 8
1 2 3 4 5 6 7 -- -- 8 9 10 11 12 13 14
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
VOUT CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 VREF VSS CS SI SO SCK VDD
Analog Output Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input External Reference Pin Negative Power Supply SPI Chip Select SPI Serial Data Input SPI Serial Data Output SPI Clock Input Positive Power Supply
3.1
Analog Output
3.4
Power Supply (VSS and VDD)
The output pin (VOUT) is a low-impedance voltage source. The selected gain (G), selected input (CH0CH7) and voltage at VREF determine its value.
3.2
Analog Inputs (CH0 thru CH7)
The positive power supply pin (VDD) is 2.5V to 5.5V higher than the negative power supply pin (VSS). For normal operation, the other pins are between VSS and VDD. Typically, these parts are used in a single (positive) supply configuration. In this case, VSS is connected to ground and VDD is connected to the supply. VDD will need a local bypass capacitor (0.1 F) at the VDD pin. It can share a bulk capacitor with nearby analog parts (typically 2.2 F to 10 F within 4 inches (100 mm) of the VDD pin.
The inputs CH0 through CH7 connect to the signal sources. They are high-impedance CMOS inputs with low bias currents. The internal MUX selects which one is amplified to the output.
3.3
External Reference Voltage (VREF)
The V REF pin should be at a voltage between VSS and VDD (the MCP6S22 has VREF tied internally to V SS). The voltage at this pin shifts the output voltage.
3.5
Digital Inputs
The SPI interface inputs are: Chip Select (CS), Serial Input (SI) and Serial Clock (SCK). These are Schmitttriggered, CMOS logic inputs.
3.6
Digital Output
The MCP6S26 and MCP6S28 devices have a SPI interface serial output (SO) pin. This is a CMOS pushpull output and does not ever go High-Z. Once the device is deselected (CS goes high), SO is forced low. This feature supports daisy chaining, as explained in Section 5.3, "Daisy Chain Configuration".
2003 Microchip Technology Inc.
DS21117A-page 15
MCP6S21/2/6/8
4.0 ANALOG FUNCTIONS
4.1 Input MUX
The MCP6S21/2/6/8 family of Programmable Gain Amplifiers (PGA) are based on simple analog building blocks (see Figure 4-1). Each of these blocks will be explained in more detail in the following sub-sections.
VDD CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CS SI SO SCK + MUX RF Gain Switches SPITM Logic POR VSS VREF 8 RG Resistor Ladder (R LAD)
The MCP6S21 has one input, the MCP6S22 and MCP6S25 have two inputs, the MCP6S26 has six inputs and the MCP6S28 has eight inputs (see Figure 4-1). For the lowest input current, float unused inputs. Tying these pins to a voltage near the used channels also works well. For simplicity, they can be tied to VSS or VDD, but the input current may increase. The one channel MCP6S21 has the lowest input bias current, while the eight channel MCP6S28 has the highest. There is about a 2:1 ratio in IB between these parts.
VOUT
4.2
Internal Op Amp
The internal op amp provides the right combination of bandwidth, accuracy and flexibility.
4.2.1
COMPENSATION CAPACITORS
MCP6S21-One input (CH0), no SO pin MCP6S22-Two inputs (CH0, CH1), V REF tied internally to VSS, no SO pin MCP6S26-Six inputs (CH0 to CH5) MCP6S28-Eight inputs (CH0 to CH7)
The internal op amp has three compensation capacitors connected to a switching network. They are selected to give good small signal bandwidth at high gains, and good slew rate (full power bandwidth) at low gains. The change in bandwidth as gain changes is between 2 MHz and 12 MHz. Refer to Table 4-1 for more information.
FIGURE 4-1:
PGA Block Diagram.
TABLE 4-1:
Gain (V/V)
GAIN VS. INTERNAL COMPENSATION CAPACITOR
Internal Compensation Capacitor Typical GBWP (MHz) Typical SR (V/s) Typical FPBW (MHz) Typical BW (MHz) 12 6 10 7 2.4 2.0 5 2.0
1 Large 12 4.0 0.30 2 Large 12 4.0 0.30 4 Medium 20 11 0.70 5 Medium 20 11 0.70 8 Medium 20 11 0.70 10 Medium 20 11 0.70 16 Small 64 22 1.6 32 Small 64 22 1.6 Note 1: FPBW is the Full Power Bandwidth. These numbers are based on VDD = 5.0V. 2: No changes in DC performance (e.g., V OS) accompany a change in compensation capacitor. 3: BW is the closed-loop, small signal -3 dB bandwidth.
DS21117A-page 16
2003 Microchip Technology Inc.
MCP6S21/2/6/8
4.2.2 RAIL-TO-RAIL INPUT
4.3
Resistor Ladder
The input stage of the internal op amp uses two differential input stages in parallel; one operates at low V IN (input voltage), while the other operates at high VIN. With this topology, the internal inputs can operate to 0.3V past either supply rail. The input offset voltage is measured at both VIN = VSS - 0.3V and VDD + 0.3V to ensure proper operation. The transition between the two input stages occurs when VIN VDD - 1.5V. For the best distortion and gain linearity, avoid this region of operation.
The resistor ladder shown in Figure 4-1 (RLAD = RF + RG) sets the gain. Placing the gain switches in series with the inverting input reduces the parasitic capacitance, distortion and gain mismatch. RLAD is an additional load on the output of the PGA and causes additional current draw from the supplies. In Shutdown mode, RLAD is still attached to the OUT and VREF pins. Thus, these pins and the internal amplifier's inverting input are all connected through RLAD and the output is not high-Z (unlike the external op amp). While RLAD contributes to the output noise, its effect is small. Refer to Figure 2-12.
4.2.3
RAIL-TO-RAIL OUTPUT
The Maximum Output Voltage Swing is the maximum swing possible under a particular output load. According to the specification table, the output can reach within 60 mV of either supply rail when RL = 10 k and VREF = VDD/2. See Figure 2-21 for typical performance under other conditions.
4.4
Shutdown Mode
4.2.4
INPUT VOLTAGE AND PHASE REVERSAL
These PGAs use a software shutdown command. When the SPI interface sends a shutdown command, the internal op amp is shut down and its output placed in a high-Z state. The resistive ladder is always connected between VREF and V OUT; even in shutdown. This means that the output resistance will be on the order of 5 k and there will be a path for output signals to appear at the input. The Power-on Reset (POR) circuitry will temporarily place the part in shutdown when activated. See Section 5.4, "Power-On Reset", for details.
The amplifier family is designed with CMOS input devices. It is designed to not exhibit phase inversion when the input pins exceed the supply voltages. Figure 2-34 shows an input voltage exceeding both supplies with no resulting phase inversion. The maximum voltage that can be applied to the input pins (CHX) is VSS - 0.3V to VDD + 0.3V. Voltages on the inputs that exceed this absolute maximum rating can cause excessive current to flow in or out of the input pins. Current beyond 2 mA can cause possible reliability problems. Applications that exceed this rating must be externally limited with an input resistor, as shown in Figure 4-2.
RIN CHX VIN MCP6S2X VOUT
( Maximum expected V IN ) - V DD R IN -----------------------------------------------------------------------------2 mA V SS - ( Minimum expected V IN ) R IN --------------------------------------------------------------------------2 mA
FIGURE 4-2: into an input pin.
R IN limits the current flow
2003 Microchip Technology Inc.
DS21117A-page 17
MCP6S21/2/6/8
5.0 DIGITAL FUNCTIONS
The MCP6S21/2/6/8 PGAs use a standard SPI compatible serial interface to receive instructions from a controller. This interface is configured to allow daisy chaining with other SPI devices. There is an internal POR (Power On Reset) that resets the registers under low power conditions. CS is raised after one word (16 bits) to implement the desired changes. Section 5.3, "Registers", covers applications using multiple 16-bit words. SO goes low after CS goes high; it has a push-pull output that does not go into a high-Z state. The MCP6S21/2/6/8 devices operate in SPI Modes 0,0 and 1,1. In 0,0 mode, the clock idles in the low state (Figure 5-1) and, in 1,1 mode, the clock idles in the high state (Figure 5-2). In both modes, SI data is loaded into the PGA on the rising edge of SCK and SO data is clocked out on the falling edge of SCK. In 0,0 mode, the falling edge of CS also acts as the first falling edge of SCK (see Figure 5-1). There must be multiples of 16 clocks (SCK) while CS is low or commands will abort (see Section 5.3, "Registers").
5.1
SPI Timing
Chip Select (CS) toggles low to initiate communication with these devices. The first byte of each SI word (two bytes long) is the instruction byte, which goes into the Instruction Register. The Instruction Register points the second byte to its destination. In a typical application, CS 1 SCK 2 3 4 5 6 7 8
9
10
11
12
13
14
15
16
SI bit 7 bit 0 bit 7 bit 0 Data Byte 10 11 12 13 14 15 16 Data Byte
2003 Microchip Technology Inc.
Instruction Byte SO (first 16 bits out are always zeros)
FIGURE 5-1:
CS
Serial bus sequence for the PGA; SPI 0,0 mode (see Figure 1-5).
1 SCK
2
3
4
5
6
7
8
9
SI bit 7 bit 0 bit 7 bit 0
Instruction Byte SO (first 16 bits out are always zeros)
FIGURE 5-2:
Serial bus sequence for the PGA; SPI 1,1 mode (see Figure 1-6).
DS21117A-page 18
MCP6S21/2/6/8
5.2 Registers
The analog functions are programmed through the SPI interface using 16-bit words (see Figure 5-1 and Figure 5-2). This data is sent to two of three 8-bit registers: Instruction Register (Register 5-1), Gain Register (Register 5-2) and Channel Register (Register 5-3). The power-up defaults for these three registers are: * Instruction Register: 000x xxx0 * Gain Register: xxxx x000 * Channel Register: xxxx x000 Thus, these devices are initially programmed with the Instruction Register set for NOP (no operation), a gain of +1 V/V and CH0 as the input channel.
5.2.1
INSTRUCTION REGISTER
The Instruction Register has 3 command bits and 1 indirect address bit; see Register 5-1. The command bits include a NOP (000) to support daisy chaining (see Section 5.3, "Registers"); the other NOP commands shown should not be used (they are reserved for future use). The device is brought out of Shutdown mode when a valid command, other than NOP or Shutdown, is sent and CS is raised.
REGISTER 5-1:
INSTRUCTION REGISTER
W-0 M2 bit 7 W-0 M1 W-0 M0 U-x -- U-x -- U-x -- U-x -- W-0 A0 bit 0
bit 7-5
M2-M0: Command Bits 000 = NOP (Default) (Note 1) 001 = PGA enters Shutdown Mode as soon as a full 16-bit word is sent and CS is raised. (Notes 1 and 2) 010 = Write to register. 011 = NOP (reserved for future use) (Note 1) 1XX = NOP (reserved for future use) (Note 1) Unimplemented: Read as `0' (reserved for future use) A0: Indirect Address Bit 1 = Addresses the Channel Register 0 = Addresses the Gain Register (Default) Note 1: All other bits in the 16-bit word (including A0) are "don't cares". 2: The device exits Shutdown mode when a valid command (other than NOP or Shutdown) is sent and CS is raised; that valid command will be executed. Shutdown does not toggle. Legend: R = Readable bit -n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
bit 4-1 bit 0
2003 Microchip Technology Inc.
DS21117A-page 19
MCP6S21/2/6/8
5.2.2 SETTING THE GAIN
The amplifier can be programmed to produce binary and decimal gain settings between +1 V/V and +32 V/V. Register 5-2 shows the details. At the same time, different compensation capacitors are selected to optimize the bandwidth vs. slew rate trade-off (see Table 4-1).
REGISTER 5-2:
GAIN REGISTER
U-x -- bit 7 U-x -- U-x -- U-x -- U-x -- W-0 G2 W-0 G1 W-0 G0 bit 0
bit 7-3 bit 2-0
Unimplemented: Read as `0' (reserved for future use) G2-G0: Gain Select Bits 000 = Gain of +1 (Default) 001 = Gain of +2 010 = Gain of +4 011 = Gain of +5 100 = Gain of +8 101 = Gain of +10 110 = Gain of +16 111 = Gain of +32 Legend: R = Readable bit -n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
DS21117A-page 20
2003 Microchip Technology Inc.
MCP6S21/2/6/8
5.2.3 CHANGING THE CHANNEL
If the instruction register is programmed to address the channel register, the multiplexed inputs of the MCP6S22, MCP6S26 and MCP6S28 can be changed per Register 5-3.
REGISTER 5-3:
CHANNEL REGISTER
U-x -- bit 7 U-x -- U-x -- U-x -- U-x -- W-0 C2 W-0 C1 W-0 C0 bit 0
bit 7-3 bit 2-0
Unimplemented: Read as `0' (reserved for future use) C2-C0: Channel Select Bits MCP6S21 000 = CH0 (Default) 001 = CH0 001 = CH0 011 = CH0 100 = CH0 101 = CH0 110 = CH0 111 = CH0 Legend: R = Readable bit -n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown MCP6S22 CH0 (Default) CH1 CH0 CH1 CH0 CH1 CH0 CH1 MCP6S26 CH0 (Default) CH1 CH2 CH3 CH4 CH5 CH0 CH0 MCP6S28 CH0 (Default) CH1 CH2 CH3 CH4 CH5 CH6 CH7
2003 Microchip Technology Inc.
DS21117A-page 21
MCP6S21/2/6/8
5.2.4 SHUTDOWN COMMAND
The software Shutdown command allows the user to put the amplifier into a low power mode (see Register 5-1). In this shutdown mode, most pins are high impedance (Section 4.4, "Shutdown Mode", and Section 5.1, "SPI Timing", cover the exceptions at pins VREF, VOUT and SO). Once the PGA has entered shutdown mode, it will remain in this mode until either a valid command is sent to the device (other than NOP or Shutdown), or the device is powered down and back up again. The internal registers maintain their values while in shutdown. Once brought out of shutdown mode, the part comes back to its previous state (see Section 5.4 for exceptions to this rule). This makes it possible to bring the device out of shutdown mode using one command; send a command to select the current channel (or gain) and the device will exit shutdown with the same state that existed before shutdown. The example in Figure 5-3 shows a daisy chain configuration with two devices, although any number of devices can be configured this way. The MCP6S21 and MCP6S22 can only be used at the far end of the daisy chain because they do not have a serial data out (SO) pin. As shown in Figure 5-4 and Figure 5-5, both SI and SO data are sent in 16-bit (2 byte) words. These devices abort any command that is not a multiple of 16 bits. When using the daisy chain configuration, the maximum clock speed possible is reduced to 5.8 MHz because of the SO pin's propagation delay (see Electrical Specifications). The internal SPI shift register is automatically loaded with zeros whenever CS goes high (a command is executed). Thus, the first 16-bits out of the SO pin once CS line goes low are always zeros. This means that the first command loaded into the next device in the daisy chain is a NOP. This feature makes it possible to send shorter command and data byte strings when the farthest devices do not need to change. For example, if there were three devices on the chain and only the middle device needed changing, only 32 bytes of data need to be transmitted (for the first and middle devices), and the last device on the chain would receive a NOP when the CS pin is raised to execute the command.
5.3
Daisy Chain Configuration
Multiple devices can be connected in a daisy chain configuration by connecting the SO pin from one device to the SI pin on the next device and using common SCK and CS lines (Figure 5-3). This approach reduces PCB layout complexity.
PICmicro Microcontroller
CS SCK (R) SO
CS SCK SI
SO
CS SCK SI
SO
Device 1
Device 2
1. 2. 3.
Set CS low. Clock out the instruction and data for Device 2 (16 clocks) to Device 1. Device 1 automatically clocks out all zeros (first 16 clocks) to Device 2.
Device 1 00100000 00000000
Device 2 00000000 00000000
4. 5.
6.
Clock out the instruction and data for Device 1 (16 clocks) to Device 1. Device 1 automatically shifts data from Device 1 to Device 2 (16 clocks). Raise CS.
Device 1 01000001 00000111
Device 2 00100000 00000000
FIGURE 5-3:
Daisy Chain Configuration.
DS21117A-page 22
2003 Microchip Technology Inc.
MCP6S21/2/6/8
CS 1 2 3 4 5 6 7 8 9 10111213141516 SCK 1 2 3 4 5 6 7 8 9 10111213141516
SI bit 7 bit 0 bit 7 bit 0 bit 7 bit 0 bit 7 bit 0 Data Byte for Device 1 Data Byte for Device 2 Data Byte for Device 1 Data Byte for Device 2
DS21117A-page 23
Instruction Byte for Device 2
Data Byte for Device 2
Instruction Byte for Device 1
SO bit 7 bit 0 bit 7 bit 0 bit 0 bit 0 (first 16 bits out are always zeros)
Instruction Byte for Device 2
FIGURE 5-4:
CS
Serial bus sequence for daisy-chain configuration; SPI 0,0 mode.
1 2 3 4 5 6 7 8 9 10111213141516 SCK
1 2 3 4 5 6 7 8 9 10111213141516
SI bit 7 bit 0 bit 7 bit 0 bit 7 bit 0 bit 7 bit 0 bit 7
Instruction Byte for Device 2
Data Byte for Device 2
Instruction Byte for Device 1
SO bit 7 (first 16 bits out are always zeros)
Instruction Byte for Device 2
FIGURE 5-5:
Serial bus sequence for daisy-chain configuration; SPI 1,1 mode.
2003 Microchip Technology Inc.
MCP6S21/2/6/8
5.4 Power-On Reset
If the power supply voltage goes below the POR trip voltage (VDD < VPOR 1.7V), the internal POR circuit will reset all of the internal registers to their power-up defaults (this is a protection against low power supply voltages). The POR circuit also holds the part in shutdown mode while it is activated. It temporarily overrides the software shutdown status. The POR releases the shutdown circuitry once it is released (VDD > VPOR). A 0.1 F bypass capacitor mounted as close as possible to the VDD pin provides additional transient immunity.
DS21117A-page 24
2003 Microchip Technology Inc.
MCP6S21/2/6/8
6.0
6.1
APPLICATIONS INFORMATION
Changing External Reference Voltage
For CL 100 pF, a good estimate for RISO is 50. This value can be fine-tuned on the bench. Adjust RISO so that the step response overshoot and frequency response peaking are acceptable at all gains.
Figure 6-1 shows a MCP6S21 with the V REF pin at 2.5V and VDD = 5.0V. This allows the PGA to amplify signals centered on 2.5V, instead of ground-referenced signals. The voltage reference MCP1525 is buffered by a MCP6021, which gives a low output impedance reference voltage from DC to high frequencies. The source driving the V REF pin should have an output impedance of 0.1 to maintain reasonable gain accuracy. VDD VDD VIN MCP1525 2.5V REF MCP6021 1 F VDD MCP6S21 VREF VOUT
6.3
Layout Considerations
Good PC board layout techniques will help achieve the performance shown in the Electrical Characteristics and Typical Performance Curves. It will also help minimize EMC (Electro-Magnetic Compatibility) issues.
6.3.1
COMPONENT PLACEMENT
Separate circuit functions; digital from analog, low speed from high speed, and low power from high power, as this will reduce crosstalk. Keep sensitive traces short and straight, separating them from interfering components and traces. This is especially important for high frequency (low rise time) signals. Use a 0.1 F supply bypass capacitor within 0.1 inch (2.5 mm) of the V DD pin. It must connect directly to the ground plane. A multi-layer ceramic chip capacitor, or high-frequency equivalent, works best.
6.3.2
SIGNAL COUPLING
FIGURE 6-1: PGA with Different External Reference Voltage.
The input pins of the MCP6S21/2/6/8 family of operational amplifiers (op amps) are high-impedance. This makes them especially susceptible to capacitively-coupled noise. Using a ground plane helps reduce this problem. When noise is capacitively-coupled, the ground plane provides additional shunt capacitance to ground. When noise is magnetically coupled, the ground plane reduces the mutual inductance between traces. Increasing the separation between traces makes a significant difference. Changing the direction of one of the traces can also reduce magnetic coupling. It may help to locate guard traces next to the victim trace. They should be on both sides of the victim trace and be as close as possible. Connect the guard traces to the ground plane at both ends, and in the middle, of long traces.
6.2
Capacitive Load and Stability
Large capacitive loads can cause both stability problems and reduced bandwidth for the MCP6S21/2/6/8 family of PGAs (Figure 2-17 and Figure 2-18). This happens because a large load capacitance decreases the internal amplifier's phase margin and bandwidth. If the PGA drives a large capacitive load, the circuit in Figure 6-2 can be used. A small series resistor (RISO) at the VOUT improves the phase margin by making the load resistive at high frequencies. It will not, however, improve the bandwidth.
6.3.3
RISO VIN MCP6S2X VOUT CL
HIGH FREQUENCY ISSUES
Because the MCP6S21/2/6/8 PGAs reach unity gain near 64 MHz when G = 16 and 32, it is important to use good PCB layout techniques. Any parasitic coupling at high frequency might cause undesired peaking. Filtering high frequency signals (i.e., fast edge rates) can help. To minimize high frequency problems: * * * * * Use complete ground and power planes Use HF, surface mount components Provide clean supply voltages and bypassing Keep traces short and straight Try a linear power supply (e.g., an LDO)
FIGURE 6-2: Capacitive Loads.
PGA Circuit for Large
2003 Microchip Technology Inc.
DS21117A-page 25
MCP6S21/2/6/8
6.4
6.4.1
Typical Applications
GAIN RANGING
VIN + MCP6021 _ 10.0 k VOUT MCP6S21 1.11 k
Figure 6-3 shows a circuit that measures the current IX. It benefits from changing the gain on the PGA. Just as a hand-held multimeter uses different measurement ranges to obtain the best results, this circuit makes it easy to set a high gain for small signals and a low gain for large signals. As a result, the required dynamic range at the PGA's output is less than at its input (by up to 30 dB).
FIGURE 6-5:
MCP6S2X IX RS VOUT
PGA with lower gain range.
6.4.3
EXTENDED GAIN RANGE PGA
FIGURE 6-3: Wide Dynamic Range Current Measurement Circuit. 6.4.2 SHIFTED GAIN RANGE PGA
Figure 6-6 gives a +1 V/V to +1024 V/V gain range, which is much greater than the range for a single PGA (+1 V/V to +32 V/V). The first PGA provides input multiplexing capability, while the second PGA only needs one input. These devices can be daisy chained (Section 5.3, "Daisy Chain Configuration").
Figure 6-4 shows a circuit using an MCP6021 at a gain of +10 in front of an MCP6S21. This changes the overall gain range to +10 V/V to +320 V/V (from +1 V/V to +32 V/V).
VIN
MCP6S28
MCP6S21
VOUT
VIN
+ MCP6021 _ MCP6S21 VOUT
FIGURE 6-6: Range. 6.4.4
PGA with Extended Gain
MULTIPLE SENSOR AMPLIFIER
10.0 k 1.11 k
The multiple channel PGAs (except the MCP6S21) allow the user to select which sensor appears on the output (see Figure 6-7). These devices can also change the gain to optimize performance for each sensor.
FIGURE 6-4: Range.
PGA with Modified Gain
Sensor # 0 Sensor # 1 Sensor # 5
MCP6S26
VOUT
It is also easy to shift the gain range to lower gains (see Figure 6-6). The MCP6021 acts as a unity gain buffer, and the resistive voltage divider shifts the gain range down to +0.1 V/V to +3.2 V/V (from +1 V/V to +32 V/V).
FIGURE 6-7: Inputs.
PGA with Multiple Sensor
DS21117A-page 26
2003 Microchip Technology Inc.
MCP6S21/2/6/8
6.4.5 EXPANDED INPUT PGA 6.4.7 ADC DRIVER
Figure 6-8 shows cascaded MCP6S28s that provide up to 15 input channels. Obviously, Sensors #7-14 have a high total gain range available, as explained in Section 6.4.3, "Extended Gain Range". These devices can be daisy chained (Section 5.3, "Daisy Chain Configuration"). Sensors # 0-6 MCP6S28 Sensors # 7-14 MCP6S28 The family of PGA's is well suited for driving Analog-toDigital Converters (ADC). The binary gains (1, 2, 4, 8, 16 and 32) effectively add five more bits to the input range (see Figure 6-10). This works well for applications needing relative accuracy more than absolute accuracy (e.g., power monitoring). Lowpass Filter VOUT VIN MCP6S28 MCP3201 12 OUT
FIGURE 6-10: FIGURE 6-8: 6.4.6 PGA with Expanded Inputs.
PGA as an ADC Driver.
PICmicro(R) MCU WITH EXPANDED INPUT CAPABILITY
Figure 6-9 shows an MCP6S28 driving an analog input to a PICmicro(R) microcontroller. This greatly expands the input capacity of the microcontroller, while adding the ability to select the appropriate gain for each source.
At low gains, the ADC's Signal-to-Noise Ratio (SNR) will dominate since the PGAs input noise voltage density is so low (10 nV/Hz @ 10 kHz, typ.). At high gains, the PGA's noise will dominate the SNR, but its low noise supports most applications. Again, these PGAs add the flexibility of selecting the best gain for an application. The low pass filter in the block diagram reduces the integrated noise at the MCP6S28's output and serves as an anti-aliasing filter. This filter may be designed using Microchip's FilterLab(R) software, available at www.microchip.com.
VIN
MCP6S28
PICmicro(R) Microcontroller
SPITM
FIGURE 6-9: Expanded Input for a PICmicro Microcontroller.
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DS21117A-page 27
MCP6S21/2/6/8
7.0
7.1
PACKAGING INFORMATION
Package Marking Information
8-Lead PDIP (300 mil) (MCP6S21, MCP6S22) Example:
XXXXXXXX XXXXXNNN YYWW
MCP6S21 I/P256 0345
8-Lead SOIC (150 mil) (MCP6S21, MCP6S22)
Example:
XXXXXXXX XXXXYYWW NNN
MCP6S21 I/SN0345 256
8-Lead MSOP (MCP6S21, MCP6S22)
Example:
XXXXX YWWNNN
MCP6S21I 345256
Legend: XX...X YY WW NNN Note:
Customer specific information* Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information.
*
Standard marking consists of Microchip part number, year code, week code, traceability code (facility code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please check with your Microchip Sales Office.
DS21117A-page 28
2003 Microchip Technology Inc.
MCP6S21/2/6/8
Package Marking Information (Con't)
14-Lead PDIP (300 mil) (MCP6S26) Example:
XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN
MCP6S26-I/P XXXXXXXXXXXXXX 0345256
14-Lead SOIC (150 mil) (MCP6S26)
Example:
XXXXXXXXXXX XXXXXXXXXXX YYWWNNN
MCP6S26ISL XXXXXXXXXXXXXXXXXXXXXXXXX 0345256
14-Lead TSSOP (4.4mm) (MCP6S26)
Example:
XXXXXXXX YYWW NNN
MCP6S26IST 0345 256
2003 Microchip Technology Inc.
DS21117A-page 29
MCP6S21/2/6/8
Package Marking Information (Con't)
16-Lead PDIP (300 mil) (MCP6S28) Example:
XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN
MCP6S28-I/P XXXXXXXXXXXXXX 0345256
16-Lead SOIC (150 mil) (MCP6S28)
Example:
XXXXXXXXXXXXX XXXXXXXXXXXXX YYWWNNN
MCP6S28-I/SL XXXXXXXXXXXXXXXXXXXXXXXX 0345256
DS21117A-page 30
2003 Microchip Technology Inc.
MCP6S21/2/6/8
8-Lead Plastic Dual In-line (P) - 300 mil (PDIP)
E1
D 2 n 1 E
A
A2
c
L A1
eB
B1 p B
Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic
Units Dimension Limits n p A A2 A1 E E1 D L c B1 B eB
MIN
INCHES* NOM 8 .100 .155 .130 .313 .250 .373 .130 .012 .058 .018 .370 10 10
MAX
MIN
.140 .115 .015 .300 .240 .360 .125 .008 .045 .014 .310 5 5
.170 .145 .325 .260 .385 .135 .015 .070 .022 .430 15 15
MILLIMETERS NOM 8 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 9.14 9.46 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10
MAX
4.32 3.68 8.26 6.60 9.78 3.43 0.38 1.78 0.56 10.92 15 15
Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018
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DS21117A-page 31
MCP6S21/2/6/8
8-Lead Plastic Small Outline (SN) - Narrow, 150 mil (SOIC)
E E1
p D 2 B n 1
h 45
c A
A2
L A1
Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic
Units Dimension Limits n p A A2 A1 E E1 D h L c B
MIN
.053 .052 .004 .228 .146 .189 .010 .019 0 .008 .013 0 0
INCHES* NOM 8 .050 .061 .056 .007 .237 .154 .193 .015 .025 4 .009 .017 12 12
MAX
MIN
.069 .061 .010 .244 .157 .197 .020 .030 8 .010 .020 15 15
MILLIMETERS NOM 8 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 6.02 3.71 3.91 4.80 4.90 0.25 0.38 0.48 0.62 0 4 0.20 0.23 0.33 0.42 0 12 0 12
MAX
1.75 1.55 0.25 6.20 3.99 5.00 0.51 0.76 8 0.25 0.51 15 15
Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057
DS21117A-page 32
2003 Microchip Technology Inc.
MCP6S21/2/6/8
8-Lead Plastic Micro Small Outline Package (MS) (MSOP)
p
E E1
D 2 B n 1
A c A1
A2
(F)
L
Units Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Foot Length Footprint (Reference) Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom *Controlling Parameter Significant Characteristic Notes: Dimension Limits n p A A2 A1 E E1 D L F c B .030 .002 .184 .114 .114 .016 .035 0 .004 .010 MIN
INCHES NOM 8 .026 .044 .034 .193 .118 .118 .022 .037 .006 .012 7 7 .038 .006 .200 .122 .122 .028 .039 6 .008 .016 MAX MIN
MILLIMETERS* NOM 0.65 1.18 0.76 0.05 4.67 2.90 2.90 0.40 0.90 0 0.10 0.25 0.15 0.30 7 7 4.90 3.00 3.00 0.55 0.95 0.86 0.97 0.15 .5.08 3.10 3.10 0.70 1.00 6 0.20 0.40 MAX 8
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. Drawing No. C04-111
2003 Microchip Technology Inc.
DS21117A-page 33
MCP6S21/2/6/8
14-Lead Plastic Dual In-line (P) - 300 mil (PDIP)
E1
D
2 n 1
E A A2
c A1 eB B1 B p
L
Number of Pins Pitch Top to Seating Plane A .140 .170 Molded Package Thickness A2 .115 .145 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .300 .313 .325 Molded Package Width E1 .240 .250 .260 Overall Length D .740 .750 .760 Tip to Seating Plane L .125 .130 .135 c Lead Thickness .008 .012 .015 Upper Lead Width B1 .045 .058 .070 Lower Lead Width B .014 .018 .022 Overall Row Spacing eB .310 .370 .430 Mold Draft Angle Top 5 10 15 Mold Draft Angle Bottom 5 10 15 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-005
Units Dimension Limits n p
MIN
INCHES* NOM 14 .100 .155 .130
MAX
MIN
MILLIMETERS NOM 14 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 18.80 19.05 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10
MAX
4.32 3.68 8.26 6.60 19.30 3.43 0.38 1.78 0.56 10.92 15 15
DS21117A-page 34
2003 Microchip Technology Inc.
MCP6S21/2/6/8
14-Lead Plastic Small Outline (SL) - Narrow, 150 mil (SOIC)
E E1
p
D
2 B n 1 h 45 c A A2
L Units Dimension Limits n p A A2 A1 E E1 D h L c B INCHES* NOM 14 .050 .061 .056 .007 .236 .154 .342 .015 .033 4 .009 .017 12 12 MILLIMETERS NOM 14 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 5.99 3.81 3.90 8.56 8.69 0.25 0.38 0.41 0.84 0 4 0.20 0.23 0.36 0.42 0 12 0 12 A1
MIN
MAX
MIN
MAX
Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic
.053 .052 .004 .228 .150 .337 .010 .016 0 .008 .014 0 0
.069 .061 .010 .244 .157 .347 .020 .050 8 .010 .020 15 15
1.75 1.55 0.25 6.20 3.99 8.81 0.51 1.27 8 0.25 0.51 15 15
Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-065
2003 Microchip Technology Inc.
DS21117A-page 35
MCP6S21/2/6/8
14-Lead Plastic Thin Shrink Small Outline (ST) - 4.4 mm (TSSOP)
E E1 p
D 2 n B 1
A c
L A1 A2
Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Molded Package Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic
Units Dimension Limits n p A A2 A1 E E1 D L c B1
MIN
INCHES NOM 14 .026 .035 .004 .251 .173 .197 .024 4 .006 .010 5 5
MAX
MIN
.033 .002 .246 .169 .193 .020 0 .004 .007 0 0
.043 .037 .006 .256 .177 .201 .028 8 .008 .012 10 10
MILLIMETERS* NOM MAX 14 0.65 1.10 0.85 0.90 0.95 0.05 0.10 0.15 6.25 6.38 6.50 4.30 4.40 4.50 4.90 5.00 5.10 0.50 0.60 0.70 0 4 8 0.09 0.15 0.20 0.19 0.25 0.30 0 5 10 0 5 10
Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. JEDEC Equivalent: MO-153 Drawing No. C04-087
DS21117A-page 36
2003 Microchip Technology Inc.
MCP6S21/2/6/8
16-Lead Plastic Dual In-line (P) - 300 mil (PDIP)
E1
D
2 n E 1
A
A2
c eB A1 B1 B Units Dimension Limits n p INCHES* NOM 16 .100 .140 .155 .115 .130 .015 .300 .313 .240 .250 .740 .750 .125 .130 .008 .012 .045 .058 .014 .018 .310 .370 5 10 5 10 p MILLIMETERS NOM 16 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 18.80 19.05 3.18 3.30 0.20 0.29 1.14 1.46 .036 0.46 7.87 9.40 5 10 5 10
L
MIN
MAX
MIN
MAX
Number of Pins Pitch Top to Seating Plane A .170 Molded Package Thickness .145 A2 Base to Seating Plane A1 Shoulder to Shoulder Width E .325 Molded Package Width E1 .260 Overall Length D .760 Tip to Seating Plane L .135 c Lead Thickness .015 Upper Lead Width B1 .070 Lower Lead Width B .022 eB Overall Row Spacing .430 Mold Draft Angle Top 15 Mold Draft Angle Bottom 15 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-017
4.32 3.68 8.26 6.60 19.30 3.43 0.38 1.78 0.56 10.92 15 15
2003 Microchip Technology Inc.
DS21117A-page 37
MCP6S21/2/6/8
16-Lead Plastic Small Outline (SL) - Narrow 150 mil (SOIC)
E E1
p
D
2 B n 1 h 45 c A A2
L Units Dimension Limits n p A A2 A1 E E1 D h L c B INCHES* NOM 16 .050 .053 .061 .052 .057 .004 .007 .228 .237 .150 .154 .386 .390 .010 .015 .016 .033 0 4 .008 .009 .013 .017 0 12 0 12 MILLIMETERS NOM 16 1.27 1.35 1.55 1.32 1.44 0.10 0.18 5.79 6.02 3.81 3.90 9.80 9.91 0.25 0.38 0.41 0.84 0 4 0.20 0.23 0.33 0.42 0 12 0 12 A1
MIN
MAX
MIN
MAX
Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic
.069 .061 .010 .244 .157 .394 .020 .050 8 .010 .020 15 15
1.75 1.55 0.25 6.20 3.99 10.01 0.51 1.27 8 0.25 0.51 15 15
Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-108
DS21117A-page 38
2003 Microchip Technology Inc.
MCP6S21/2/6/8
NOTES:
2003 Microchip Technology Inc.
DS21117A-page 39
MCP6S21/2/6/8
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device -X Temperature Range /XX Package Examples:
a) b)
Device: MCP6S21: One Channel PGA MCP6S21T: One Channel PGA (Tape and Reel for SOIC and MSOP) MCP6S22: Two Channel PGA MCP6S22T: Two Channel PGA (Tape and Reel for SOIC and MSOP) MCP6S26: Six Channel PGA MCP6S26T: Six Channel PGA (Tape and Reel for SOIC and TSSOP) MCP6S28: Eight Channel PGA MCP6S28T: Eight Channel PGA (Tape and Reel for SOIC) I MS P SN SL ST = = = = = = -40C to +85C Plastic Micro Small Outline (MSOP), 8-lead Plastic DIP (300 mil Body), 8, 14, and 16-lead Plastic SOIC, (150 mil Body), 8-lead Plastic SOIC (150 mil Body), 14, 16-lead Plastic TSSOP (4.4mm Body), 14-lead
MCP6S21-I/P: One Channel PGA, PDIP package. MCP6S21-I/SN: One Channel PGA, SOIC package. MCP6S21-I/MS: One Channel PGA, MSOP package. MCP6S22-I/MS: Two Channel PGA, MSOP package. MCP6S22T-I/MS: Tape and Reel, Two Channel PGA, MSOP package. MCP6S26-I/P: Six Channel PGA, PDIP package. MCP6S26-I/SN: Six Channel PGA, SOIC package. MCP6S26T-I/ST: Tape and Reel, Six Channel PGA, TSSOP package. MCP6S28T-I/SL: Tape and Reel, Eight Channel PGA, SOIC package.
c) d) e) f) g) h) i)
Temperature Range: Package:
Sales and Support
Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
2002 Microchip Technology Inc.
DS21117A-page 39
MCP6S21/2/6/8
NOTES:
DS21117A-page 40
2002 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: * * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, KEELOQ, MPLAB, PIC, PICmicro, PICSTART, PRO MATE and PowerSmart are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Accuron, Application Maestro, dsPIC, dsPICDEM, dsPICDEM.net, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICC, PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPIC, Select Mode, SmartSensor, SmartShunt, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2003, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro (R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified.
2003 Microchip Technology Inc.
DS21117A - page 41
M
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office
2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: 480-792-7627 Web Address: http://www.microchip.com
ASIA/PACIFIC
Australia
Microchip Technology Australia Pty Ltd Marketing Support Division Suite 22, 41 Rawson Street Epping 2121, NSW Australia Tel: 61-2-9868-6733 Fax: 61-2-9868-6755
Japan
Microchip Technology Japan K.K. Benex S-1 6F 3-18-20, Shinyokohama Kohoku-Ku, Yokohama-shi Kanagawa, 222-0033, Japan Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Rocky Mountain
2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7966 Fax: 480-792-4338
Korea
Microchip Technology Korea 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea 135-882 Tel: 82-2-554-7200 Fax: 82-2-558-5934
China - Beijing
Microchip Technology Consulting (Shanghai) Co., Ltd., Beijing Liaison Office Unit 915 Bei Hai Wan Tai Bldg. No. 6 Chaoyangmen Beidajie Beijing, 100027, No. China Tel: 86-10-85282100 Fax: 86-10-85282104
Atlanta
3780 Mansell Road, Suite 130 Alpharetta, GA 30022 Tel: 770-640-0034 Fax: 770-640-0307
Singapore
Microchip Technology Singapore Pte Ltd. 200 Middle Road #07-02 Prime Centre Singapore, 188980 Tel: 65-6334-8870 Fax: 65-6334-8850
Boston
2 Lan Drive, Suite 120 Westford, MA 01886 Tel: 978-692-3848 Fax: 978-692-3821
China - Chengdu
Microchip Technology Consulting (Shanghai) Co., Ltd., Chengdu Liaison Office Rm. 2401-2402, 24th Floor, Ming Xing Financial Tower No. 88 TIDU Street Chengdu 610016, China Tel: 86-28-86766200 Fax: 86-28-86766599
Taiwan
Microchip Technology (Barbados) Inc., Taiwan Branch 11F-3, No. 207 Tung Hua North Road Taipei, 105, Taiwan Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
Chicago
333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 630-285-0071 Fax: 630-285-0075
Dallas
4570 Westgrove Drive, Suite 160 Addison, TX 75001 Tel: 972-818-7423 Fax: 972-818-2924
China - Fuzhou
Microchip Technology Consulting (Shanghai) Co., Ltd., Fuzhou Liaison Office Unit 28F, World Trade Plaza No. 71 Wusi Road Fuzhou 350001, China Tel: 86-591-7503506 Fax: 86-591-7503521
EUROPE
Austria
Microchip Technology Austria GmbH Durisolstrasse 2 A-4600 Wels Austria Tel: 43-7242-2244-399 Fax: 43-7242-2244-393
Detroit
Tri-Atria Office Building 32255 Northwestern Highway, Suite 190 Farmington Hills, MI 48334 Tel: 248-538-2250 Fax: 248-538-2260
China - Hong Kong SAR
Microchip Technology Hongkong Ltd. Unit 901-6, Tower 2, Metroplaza 223 Hing Fong Road Kwai Fong, N.T., Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431
Kokomo
2767 S. Albright Road Kokomo, Indiana 46902 Tel: 765-864-8360 Fax: 765-864-8387
Denmark
Microchip Technology Nordic ApS Regus Business Centre Lautrup hoj 1-3 Ballerup DK-2750 Denmark Tel: 45 4420 9895 Fax: 45 4420 9910
China - Shanghai
Microchip Technology Consulting (Shanghai) Co., Ltd. Room 701, Bldg. B Far East International Plaza No. 317 Xian Xia Road Shanghai, 200051 Tel: 86-21-6275-5700 Fax: 86-21-6275-5060
Los Angeles
18201 Von Karman, Suite 1090 Irvine, CA 92612 Tel: 949-263-1888 Fax: 949-263-1338
France
Microchip Technology SARL Parc d'Activite du Moulin de Massy 43 Rue du Saule Trapu Batiment A - ler Etage 91300 Massy, France Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
San Jose
Microchip Technology Inc. 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408-436-7950 Fax: 408-436-7955
China - Shenzhen
Microchip Technology Consulting (Shanghai) Co., Ltd., Shenzhen Liaison Office Rm. 1812, 18/F, Building A, United Plaza No. 5022 Binhe Road, Futian District Shenzhen 518033, China Tel: 86-755-82901380 Fax: 86-755-82966626
Toronto
6285 Northam Drive, Suite 108 Mississauga, Ontario L4V 1X5, Canada Tel: 905-673-0699 Fax: 905-673-6509
Germany
Microchip Technology GmbH Steinheilstrasse 10 D-85737 Ismaning, Germany Tel: 49-089-627-144-100 Fax: 49-089-627-144-44
China - Qingdao
Rm. B505A, Fullhope Plaza, No. 12 Hong Kong Central Rd. Qingdao 266071, China Tel: 86-532-5027355 Fax: 86-532-5027205
Italy
Microchip Technology SRL Via Quasimodo, 12 20025 Legnano (MI) Milan, Italy Tel: 39-0331-742611 Fax: 39-0331-466781
India
Microchip Technology Inc. India Liaison Office Marketing Support Division Divyasree Chambers 1 Floor, Wing A (A3/A4) No. 11, O'Shaugnessey Road Bangalore, 560 025, India Tel: 91-80-2290061 Fax: 91-80-2290062
United Kingdom
Microchip Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44 118 921 5869 Fax: 44-118 921-5820
02/12/03
DS21117A-page 42
2003 Microchip Technology Inc.

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